Maximizes compute efficiency and performance of AI infrastructure

• Increases bandwidth, power efficiency, and XPU utilization rates
• Reduces costs and latency of inference
• Facilitates disaggregated memory architectures for efficient, scalable large language model (LLM) token delivery

Key Features

• UCIe-based optical I/O chiplets at 10x higher bandwidth than conventional copper and optical pluggables

• Silicon photonics on mature high-volume CMOS manufacturing and packaging process nodes

• Enables XPUs and switches to interconnect across tens of meters with low latency, low power, and high throughput

• Industry-defining multi-wavelength, multi-port high-power laser source

• Optimized for reliability, availability and serviceability (RAS)

• Scalable design in industry-standard ELSFP form factor